The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Jul. 27, 2023
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Radhakrishnan L. Nagarajan, San Jose, CA (US);

Mark Patterson, San Jose, CA (US);

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/43 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
G02B 6/43 (2013.01); G02B 6/4214 (2013.01); G02B 6/4246 (2013.01); G02B 6/4257 (2013.01); G02B 6/426 (2013.01); G02B 6/4261 (2013.01);
Abstract

A co-packaged electro-optical module includes: a first planar light circuit (PLC) block; a silicon photonics chip electrically coupled to one or more chips; a splitter embedded in the first PLC block and to receive laser light from an optical fiber, to split the laser light into two portions, and to provide respective portions of the laser light to two planar waveguides; a planar surface of the silicon photonics chip to receive the portions of the laser light from the two planar waveguides in a direction perpendicular to the planar surface; modulators embedded in the silicon photonics chip and to modulate the portions of the laser light; a side edge of the silicon photonics chip extending perpendicular to the planar surface and to output the modulated portions of the laser light; and a second PLC block coupled to the side edge and to transmit the modulated portions of the laser light.


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