The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2025
Filed:
Dec. 03, 2024
Applicant:
Sumco Corporation, Tokyo, JP;
Inventor:
Masayuki Miura, Tokyo, JP;
Assignee:
SUMCO CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B32B 3/10 (2006.01); B32B 3/20 (2006.01); C30B 15/20 (2006.01); C30B 25/20 (2006.01); C30B 29/06 (2006.01); C30B 30/04 (2006.01); H10D 62/60 (2025.01);
U.S. Cl.
CPC ...
C30B 25/20 (2013.01); B32B 3/10 (2013.01); B32B 3/20 (2013.01); C30B 15/203 (2013.01); C30B 29/06 (2013.01); C30B 30/04 (2013.01); H10D 62/60 (2025.01);
Abstract
An epitaxial silicon wafer comprises a silicon wafer in which the entire surface, excluding an edge region from the outermost edge to 2 mm inward, is a COP region, and an epitaxial silicon layer formed on the surface of the silicon wafer. The average COP size in the peripheral region, located within 5 mm inward from the outermost edge of the silicon wafer, is 75 nm or less.