The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Feb. 27, 2024
Applicant:

Lextar Electronics Corporation, Hsinchu, TW;

Inventors:

Chih-Hao Lin, Hsinchu, TW;

Jo-Hsiang Chen, Hsinchu, TW;

Shih-Lun Lai, Hsinchu, TW;

Min-Che Tsai, Hsinchu, TW;

Jian-Chin Liang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10H 20/857 (2025.01); H10H 20/01 (2025.01); H10H 20/855 (2025.01);
U.S. Cl.
CPC ...
H10H 20/857 (2025.01); H10H 20/01 (2025.01); H10H 20/855 (2025.01); H10H 20/0363 (2025.01); H10H 20/0364 (2025.01);
Abstract

The light emitting diode packaging structure includes a flexible substrate, micro light emitting elements disposed on the flexible substrate, a conductive pad, a redistribution layer, and an electrode pad. The micro light emitting elements have a first surface facing to the flexible substrate and a second surface opposite to the first surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting elements. The redistribution layer covers the micro light emitting elements and the conductive pad. The redistribution layer includes an insulating layer and a circuit layer embedded in the insulating layer. The circuit layer is electrically connected to the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer.


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