The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jul. 30, 2021
Applicants:

Gree Electric Appliances, Inc.of Zhuhai, Zhuhai, CN;

Edgeless Semiconductor Co. Ltd. of Zhuhai, Zhuhai, CN;

Inventors:

Daokun Chen, Zhuhai, CN;

Bo Shi, Zhuhai, CN;

Yiren Lin, Zhuhai, CN;

Dan Zeng, Zhuhai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/00 (2025.01); H10D 12/01 (2025.01); H10D 62/10 (2025.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H10D 84/146 (2025.01); H10D 12/031 (2025.01); H10D 62/127 (2025.01); H10D 62/8325 (2025.01);
Abstract

Some embodiments of the present disclosure provide a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method. The transistor includes first and second cells which jointly include a drain electrode layer, an ohmic contact layer, a substrate layer, an epitaxial layer, an interlayer dielectric layer, and a source electrode layer, the first cell further includes a first deep well region, a second deep well region, a first shallow well region, a second shallow well region, a two first source region, a two second source region, a first gate oxide layer, and a first polysilicon gate, and the second cell further includes a third deep well region, a fourth deep well region, a third shallow well region, a fourth shallow well region, a second gate oxide layer, a third gate oxide layer, a second polysilicon gate, and a third polysilicon gate.


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