High electron mobility transistor with reduced access resistance and method for manufacturing a high electron mobility transistor with reduced access resistance

Abstract

A high electron mobility transistor includes a stack of layers including a passivation layer and a heterojunction including a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; an n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at the level of a recess formed in the stack of layers, the source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first and second semiconductor layers.