The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

May. 25, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Hitoshi Kunitake, Kanagawa, JP;

Takayuki Ikeda, Kanagawa, JP;

Takahiro Fukutome, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01);
U.S. Cl.
CPC ...
H10B 12/00 (2023.02); H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01);
Abstract

A small-size semiconductor device is provided. The semiconductor device includes a first layer, a second layer, and a third layer formed over a substrate. A first transistor included in the first layer includes a first semiconductor layer containing Si. A second transistor included in the second layer includes a second semiconductor layer containing Ga. A third transistor included in the third layer includes a third semiconductor layer containing at least one of In and Zn. The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate. The third semiconductor layer of the third transistor is formed above the first semiconductor layer and the second semiconductor layer.


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