The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jun. 21, 2023
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Sheng Chen, Shenzhen, CN;

Theng Tee Yeo, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01);
Abstract

A multi-phase clock generation circuit is configured to generate a multi-phase non-overlapping clock signal and includes a loop structure, where input ends and output ends of a plurality of logic gates are electrically coupled head to tail to form the loop structure; and a plurality of latches configured to latch signals at the input ends of the logic gates. The multi-phase clock generation circuit performs a logical operation based on selection signals and clock signals that are received at the logic gates, latches data of upper-stage logic gates that is received at logic gates in a loop through the latches, and outputs multi-phase non-overlapping clock signals through the output ends of the logic gates.


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