The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jun. 08, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Si Yun Kim, Icheon-si, KR;

Kang Hun Kim, Icheon-si, KR;

Jun Yong Song, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/78 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/48227 (2013.01);
Abstract

A semiconductor device includes a chip body; a circuit layer over the chip body; an upper insulating layer over the circuit layer; a chip metal layer over the upper insulating layer, the chip metal layer including a pad portion; a passivation layer over the chip metal layer; a lower redistribution insulating layer over the passivation layer, the pad portion of the chip metal layer left exposed by the passivation layer and the lower redistribution insulating layer; a redistribution bonding interconnection over the lower redistribution insulating layer; and an upper redistribution insulating layer over the lower redistribution insulating layer. The redistribution bonding interconnection includes a pad connection portion electrically connected to the pad portion of the chip metal layer; a horizontal extension portion extending from the pad connection portion to a side surface of the chip body; a vertical extension portion disposed over the side surface of the chip body, the vertical extension portion extending downward from a side end portion of the horizontal extension portion; and a bonding portion disposed over the side surface of the chip body. The bonding portion is positioned at a lower end portion of the vertical extension portion.


Find Patent Forward Citations

Kim, Si. (2025). Semiconductor device having a redistribution bonding interconnection, a method of manufacturing the semiconductor device, and a chip stack package including the semiconductor device (U.S. Patent No. 12451467). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12451467

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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