The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Apr. 28, 2022
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Hsin-Han Lin, Hsinchu County, TW;

Tai-Jyun Yu, Taoyuan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 21/4857 (2013.01); H01L 23/5383 (2013.01); H01L 23/49811 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/072 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48105 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/1517 (2013.01);
Abstract

Provided are a power module and a manufacturing method thereof. The power module includes an insulating substrate, a first, a second and a third conductive layers, a first thermal interface material layer, a first and a second chips and a thermal conductive layer. The insulating substrate has a first and a second surfaces opposite to each other. The first and the second conductive layers are disposed on the first surface, and electrically separated from each other. The first thermal interface material layer is disposed on the first conductive layer. The third conductive layer is disposed on the first thermal interface material layer. The first chip is disposed on the third conductive layer and electrically connected to the third conductive layer. The second chip is disposed on the second conductive layer and electrically connected to the second conductive layer. The thermal conductive layer is disposed on the second surface.


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