Anti-radiation low-latency chip for neural network inference acceleration

Abstract

The provided is an anti-radiation low-latency chip for neural network inference acceleration. The following steps are included: deploying a neural network inference acceleration chip at a frontend of a detector, using a streaming architecture to correspond each pipeline stage to each major neural network layer, balancing a limited on-chip memory resource and support for a large-sized input, and constructing layer parallelism, channel parallelism, and convolution kernel parallelism. This application proposes to deploy an anti-radiation, low-latency, and efficient chip for convolutional neural network (CNN) inference acceleration is deployed at the frontend of the detector to improve an intelligence level of future detector hardware. To this end, a fine-grained streaming architecture, and fine-grained storage management, flexible compression and quantization, and anti-radiation digital chip design technologies are proposed to achieve a high throughput and a low on-chip memory consumption while achieving anti-radiation and low-latency inference.