The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Feb. 14, 2022
Applicant:

Efabless Corporation, San Jose, CA (US);

Inventors:

Jeffrey Dicorpo, San Carlos, CA (US);

Mohamed K. Kassem, Carlsbad, CA (US);

Michael S. Wishart, Hillsborough, CA (US);

Mohamed A. Shalan, Cairo, EG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 30/3323 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 30/3323 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 23/573 (2013.01);
Abstract

Systems and methods for assembling and developing a System-on-a-chip (SoC) by using templates and designer input data are described. One of the methods includes receiving a request for generating a design of the SoC. In response to the request, a template database is accessed to provide templates of a plurality of designs of systems-on-chips (SoCs). Each of the templates is for a technology application. The method includes receiving a selection of one of the templates. The one of the templates represents components of the SoC. The method also includes receiving a configuration file including configuration data input for the components of the SoC. The method includes compiling the configuration file and a definition file for the SoC to generate design files for the SoC.


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