The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Sep. 09, 2022
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Greg Dykema, Palo Alto, CA (US);

Maran Wilson, Palo Alto, CA (US);

Guoyao Feng, Palo Alto, CA (US);

Kuan Zhou, Palo Alto, CA (US);

Tianyu Sun, Palo Alto, CA (US);

Taylor Lee, Palo Alto, CA (US);

Kin Hing Leung, Cupertino, CA (US);

Arnav Goel, San Jose, CA (US);

Conrad Turlik, Menlo Park, CA (US);

Milad Sharif, Palo Alto, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 8/41 (2018.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 15/8038 (2013.01); G06F 8/443 (2013.01); G06F 8/447 (2013.01); G06F 8/45 (2013.01); G06F 15/7867 (2013.01); G06F 15/80 (2013.01);
Abstract

A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application. The system further comprises an archive of configuration files and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises first and second compilers that generate for the application, based on the respective first and second constraints, first and second configuration files that are stored in the archive of configuration files and adapted to be executed data-parallel compatible on respective first and second reconfigurable processors.


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