logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12446406 B1

PDFFull Text
Date of Patent:
Oct. 14, 2025

Filed:

Apr. 18, 2022

Display device

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Kwang Soo Bae, Yongin-si, KR;

Min Jeong Oh, Gimpo-si, KR;

Sang Hyun Choi, Seoul, KR;

Chaun Gi Choi, Suwon-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do, KR;

Attorney:

CANTOR COLBURN LLP

Primary Examiner:

Kyoung Lee

Int. Cl.
CPC ...
H10K 59/122 (2023.01); H10K 50/84 (2023.01); H10K 50/86 (2023.01); H10K 59/123 (2023.01); H10K 59/38 (2023.01); H10K 59/40 (2023.01); H10K 59/80 (2023.01);
U.S. Cl.
CPC ...
H10K 59/122 (2023.02); H10K 50/84 (2023.02); H10K 50/865 (2023.02); H10K 59/123 (2023.02); H10K 59/38 (2023.02); H10K 59/40 (2023.02); H10K 59/8792 (2023.02); H10K 59/8731 (2023.02);
Abstract

A display device includes a base substrate; a thin-film transistor disposed on the base substrate; a via layer disposed on the thin-film transistor and having a via hole formed therein, the via hole penetrating the via layer in a thickness direction; a first electrode disposed on the via layer and having an electrode hole formed therein, the electrode hole penetrating the first electrode in the thickness direction; a bank layer disposed on the first electrode and exposing part of a top surface of the first electrode; an emission layer on the first electrode; and a second electrode on the emission layer, wherein the first is electrically connected to the thin-film transistor through the via hole, and the bank layer includes an outer bank pattern, which overlaps with the via hole in the thickness direction, and a bank island pattern, which is disposed in the electrode hole.

Find Patent Forward Citations

Loading…