The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12446350 B1

Date of Patent:

Oct. 14, 2025

Filed:

Aug. 01, 2023

Stacked light-receiving sensor and in-vehicle imaging device

Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Ryoji Eki, Kanagawa, JP;

Assignee:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Attorney:

Wolf, Greenfield & Sacks, P.C.

Primary Examiner:

Chirag R Patel

Int. Cl.

CPC ...

H01L 27/146 (2006.01); G06F 18/214 (2023.01); G06N 3/04 (2023.01); G06V 10/147 (2022.01); G06V 10/764 (2022.01); G06V 10/82 (2022.01); G06V 20/58 (2022.01); G06V 20/59 (2022.01); H04N 7/18 (2006.01); H04N 23/617 (2023.01); H04N 25/44 (2023.01); H04N 25/709 (2023.01); H04N 25/75 (2023.01); H04N 25/79 (2023.01); H10F 39/00 (2025.01);

U.S. Cl.

CPC ...

H10F 39/809 (2025.01); G06F 18/214 (2023.01); G06N 3/04 (2013.01); G06V 10/147 (2022.01); G06V 10/764 (2022.01); G06V 10/82 (2022.01); G06V 20/58 (2022.01); G06V 20/584 (2022.01); G06V 20/597 (2022.01); H04N 7/18 (2013.01); H04N 23/617 (2023.01); H04N 25/44 (2023.01); H04N 25/709 (2023.01); H04N 25/75 (2023.01); H04N 25/79 (2023.01); H10F 39/811 (2025.01);

Abstract

Advanced processing is performed in a chip. A stacked light-receiving sensor according to an embodiment includes a first substrate (), a second substrate () bonded to the first substrate, and connection wiring () bonded to the second substrate. The first substrate includes a pixel array () in which a plurality of unit pixels are arranged in a two-dimensional matrix. The second substrate includes a converter (A) configured to convert an analog pixel signal output from the pixel array to digital image data and a processing unit () configured to perform a process for data based on the image data. At least a part of the converter is disposed on a first side in the second substrate. The processing unit is disposed on a second side opposite to the first side in the second substrate. The connection wiring is attached to a side other than the second side in the second substrate.

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