The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Sep. 02, 2022
Applicant:

Socionext Inc., Kanagawa, JP;

Inventor:

Isaya Sobue, Yokohama, JP;

Assignee:

Socionext Inc., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/07 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/80 (2025.01);
U.S. Cl.
CPC ...
H10D 84/813 (2025.01); H01L 23/5283 (2013.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01);
Abstract

A layout structure of a capacitive element using forksheet FETs is provided. A capacitive structure constituting the capacitive element includes: a first transistor having a first nanosheet extending in the X direction and a first gate interconnect extending in the Y direction and surrounding the periphery of the first nanosheet; and a second transistor having a second nanosheet extending in the X direction and a second gate interconnect extending in the Y direction and surrounding the periphery of the second nanosheet. The face of the first nanosheet closer to the second nanosheet is exposed from the first gate interconnect, and the face of the second nanosheet closer to the first nanosheet is exposed from the second gate interconnect.


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