The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Nov. 28, 2022
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Jimmy Robert Hannes Franchi, Enköping, SE;

Martin Domeij, Sollentuna, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H10D 62/109 (2025.01); H01L 21/0465 (2013.01); H10D 12/031 (2025.01); H10D 30/66 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01);
Abstract

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.


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