The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Sep. 13, 2021
Applicant:
W&wram Devices, Inc., Los Altos, CA (US);
Inventors:
Shih-Yuan Wang, Palo Alto, CA (US);
Shih-Ping Wang, Los Altos, CA (US);
Assignee:
W&Wram Devices, Inc., Los Altos, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2023.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 63/00 (2023.02); H10N 70/046 (2023.02); H10N 70/24 (2023.02); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1443 (2013.01);
Abstract
Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described in combination with stacked technology with CMOS ASIC wafters. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer. Stacking technology can be used to address incompatibility of ReRAM processing and CMOS ASICs processing.