logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12444716 B1

PDFFull Text
Date of Patent:
Oct. 14, 2025

Filed:

Mar. 17, 2023

Light-emitting diode device

Applicant:

Lextar Electronics Corporation, Hsinchu, TW;

Inventors:

Shiou-Yi Kuo, Hsinchu, TW;

Te-Chung Wang, Hsinchu, TW;

Guo-Yi Shiu, Hsinchu, TW;

Assignee:

LEXTAR ELECTRONICS CORPORATION, Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Nikolay K Yushin

Int. Cl.
CPC ...
H01L 25/075 (2006.01); H01L 25/16 (2023.01); H01L 27/12 (2006.01); H01L 33/10 (2010.01); H01L 33/62 (2010.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10H 20/814 (2025.01); H10H 20/857 (2025.01);
U.S. Cl.
CPC ...
H01L 25/0753 (2013.01); H01L 25/167 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10H 20/814 (2025.01); H10H 20/857 (2025.01);
Abstract

A light-emitting diode device including a pixel structure including first, second and third light-emitting diode chips, a passivation layer, and first, second, third and fourth circuit layers is provided. The first and second light-emitting diode chips are positioned on a top surface opposite to a light-emitting surface of the third light-emitting diode chip. First and second vertical projections of the first and second light-emitting diode chips on the top surface do not overlap each other. First and second bonding surfaces of the first and second circuit layers corresponding to openings in the passivation layer are positioned to overlap the first vertical projection and are separated from the second vertical projection. Third and fourth bonding surfaces of the third and fourth circuit layers that correspond to openings in the passivation layer are positioned to overlap the second vertical projection and are separated from the first vertical projection.

Find Patent Forward Citations

Loading…