The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Jun. 05, 2023
Applicant:

Qsigma, Inc., Sunnyvale, CA (US);

Inventors:

Earle Jennings, Santa Fe, NM (US);

George Landers, Tigard, OR (US);

Assignee:

QSigma, Inc., Denton, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/20 (2006.01); G06F 11/10 (2006.01); G06F 11/14 (2006.01); G06F 11/16 (2006.01); G06F 15/16 (2006.01); G06F 15/173 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2028 (2013.01); G06F 11/10 (2013.01); G06F 11/1443 (2013.01); G06F 11/1625 (2013.01); G06F 11/1679 (2013.01); G06F 15/161 (2013.01); G06F 15/17362 (2013.01); G06F 11/1423 (2013.01); G06F 11/202 (2013.01);
Abstract

Apparatus adapted for exascale computers are disclosed. The apparatus includes, but is not limited to at least one of: a system, data processor chip (DPC), Landing module (LM), chips including LM, anticipator chips, simultaneous multi-processor (SMP) cores, SMP channel (SMPC) cores, channels, bundles of channels, printed circuit boards (PCB) including bundles, floating point adders, accumulation managers, QUAD Link Anticipating Memory (QUADLAM), communication networks extended by coupling links of QUADLAM, log 2 calculators, exp2 calculators, log ALU, Non-Linear Accelerator (NLA), and stairways. Methods of algorithm and program development, verification and debugging are also disclosed. Collectively, embodiments of these elements disclose a class of supercomputers that obsolete Amdahl's Law, providing cabinets of petaflop performance and systems that may meet or exceed an exaflop of performance for Block LU Decomposition (Linpack).


Find Patent Forward Citations

Jennings, Earle. (2025). Simultaneous multi-processor apparatus applicable to achieving exascale performance for algorithms and program systems (U.S. Patent No. 12443495). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12443495

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…