The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Dec. 22, 2022
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Joshua Polzin, Palo Alto, CA (US);

Conrad Alexander Turlik, Palo Alto, CA (US);

Arnav Goel, Palo Alto, CA (US);

Qi Zheng, Palo Alto, CA (US);

Maran Wilson, Palo Alto, CA (US);

Neal Sanghvi, Palo Alto, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/54 (2006.01); G06F 8/41 (2018.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/544 (2013.01); G06F 8/453 (2013.01); G06F 9/5016 (2013.01); G06F 9/5038 (2013.01); G06F 2209/507 (2013.01);
Abstract

A method of pipelining execution stages of a pipelined application can comprise a Buffer Pipeline Manager (BPM) of a Buffer Pipelined Application computing System (BPAS) allocating pipeline buffers, configuring access to the pipeline buffers by stage processors of the system, transferring buffers from one stage processor to a successor stage processor, and transferring data from a buffer in one memory to a buffer in an alternative memory. The BPM can allocate the buffers based on execution parameters associated with the pipelined application and/or stage processors. The BPM can transfer data to a buffer in an alternative memory based on performance, capacity, and/or topological attributes of the memories and/or processors utilizing the memories. The BPM can perform operations of the method responsive to interfaces of a Pipeline Programming Interface (PPI). A BPAS can comprise hardware processors, physical memories, stage processors, an application execution program, the PPI, and the BPM.


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