The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

May. 03, 2023
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Wun-Ci Su, HsinChu, TW;

Jhe-Yi Lin, HsinChu, TW;

Yu-Jhao Yang, HsinChu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/505 (2013.01);
Abstract

A load balance circuit includes: a storing circuit, for storing first user field number(s) corresponding to first node(s) in a minimum full binary tree, wherein first resource unit(s) (RU(s)) corresponding to the first node(s) is smaller than or equal to an RU size; a user field number generation circuit, for generating third user field number(s) according to second user field number(s) corresponding to second node (s) in the minimum full binary tree, and generating second weight(s) according to first weight(s) corresponding to the second node(s), wherein second RU(s) corresponding to the second node(s) is greater than the RU size; and a load balance calculation circuit, for generating a plurality of user field numbers corresponding to a plurality of content channels according to the first user field number(s), the third user field number(s), the second weight(s), a load balance function and the first weight(s).


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