The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

May. 28, 2024
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Mihir Narendra Mody, Bengaluru, IN;

Kedar Satish Chitnis, Bengaluru, IN;

Kumar Desappan, Bengaluru, IN;

David Smith, Allen, TX (US);

Pramod Kumar Swami, Bengaluru, IN;

Shyam Jagannathan, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/455 (2018.01); G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06N 3/02 (2006.01); G06N 3/10 (2006.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 9/5077 (2013.01); G06F 12/00 (2013.01); G06F 12/0223 (2013.01); G06F 2009/45583 (2013.01); G06F 9/50 (2013.01); G06F 9/5022 (2013.01); G06N 3/02 (2013.01); G06N 3/10 (2013.01); G06N 20/00 (2019.01);
Abstract

Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.


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