The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Sep. 13, 2023
Applicant:

Hygon Information Technology Co., Ltd., Tianjin, CN;

Inventor:

Zehan Cui, Tianjin, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3814 (2013.01); G06F 9/30145 (2013.01); G06F 9/3818 (2013.01); G06F 9/3822 (2013.01); G06F 9/3851 (2013.01); G06F 9/3836 (2013.01);
Abstract

A decoding method of a simultaneously multi-threading processor, a processor, and a chip are provided. The method includes: fetching an instruction stream according to an instruction fetching request; segmenting the instruction stream which is fetched in response to the simultaneously multi-threading processor being in a single-threaded mode; allocating the instructions at split positions as boundaries of switching instructions queues, wherein the plurality of target instruction queues comprise instruction queues corresponding to active threads and instruction queues corresponding to inactive threads; and decoding the instructions in the plurality of target instruction queues by using a plurality of decoder groups to obtain micro-ops obtained after decoding by the decoder groups. The embodiments of the present disclosure can improve the decoding efficiency of a multi-thread processor while being compatible with multiple thread modes.


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