The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Jun. 30, 2021
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventor:

Maxim V. Kazakov, San Diego, CA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/3012 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/5016 (2013.01); G06F 9/5072 (2013.01); G06F 9/544 (2013.01); G06F 15/8007 (2013.01); G06F 15/8046 (2013.01); G06N 20/00 (2019.01);
Abstract

A processing device is provided which comprises a plurality of compute units configured to process data, a plurality of arithmetic logic units, instantiated separate from the plurality of compute units, and configured to store the data at the arithmetic logic units and perform calculations using the data and an interconnect network, connecting the arithmetic logic units and configured to provide the arithmetic logic units with shared access to the data for communication between the arithmetic logic units. The interconnect network is also configured to provide the compute units with shared access to the data for communication between the compute units.


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