The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Jun. 20, 2023
Applicant:

Sharp Display Technology Corporation, Kameyama, JP;

Inventors:

Hitoshi Takahata, Kameyama, JP;

Tohru Daitoh, Kameyama, JP;

Tetsuo Kikuchi, Kameyama, JP;

Masahiko Suzuki, Kameyama, JP;

Setsuji Nishimiya, Kameyama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01);
Abstract

An active matrix substrate includes a pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode disposed so as to face the oxide semiconductor layer with the gate insulating layer interposed therebetween, a plurality of gate lines, an interlayer insulating layer provided so as to cover the gate electrode and the plurality of gate lines, a plurality of source lines provided on the interlayer insulating layer, an upper insulating layer provided so as to cover the plurality of source lines, and an organic insulating layer provided on the upper insulating layer. The interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.


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