The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Apr. 21, 2023
Applicant:

Marvell Asia Pte Ltd, Singapore, SG;

Inventors:

Eric D. Hunt-Schroeder, Essex Junction, VT (US);

Steven Harley Lamphier, Colchester, VT (US);

Dale E. Pontius, Colchester, VT (US);

Christopher Kanyuck, Lakeland, FL (US);

Assignee:

MARVELL ASIA PTE LTD, Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/307 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); H01L 22/34 (2013.01);
Abstract

An integrated circuit device includes functional circuitry including transistors, and testing circuitry configured to test effects of different layouts of the functional circuitry, relative to physical features of the integrated circuit device, on operation of the transistors. The testing circuitry includes at least one first test circuit having a first physical relationship relative to the physical features of the integrated circuit device, at least one second test circuit having a second physical relationship, different from the first physical relationship, relative to the physical features of the integrated circuit device, and sensing circuitry for reading outputs of the at least one first test circuit and the at least one second test circuit. Imbalance circuitry is configured to apply compensation to the functional circuitry to compensate for a sensed imbalance. There may be a plurality of instances of the first test circuit, and a plurality of instances of the second test circuit.


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