The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Jun. 05, 2024
Applicant:

Analog Devices International Unlimited Company, County Limerick, IE;

Inventors:

Edward John Coyne, Athenry, IE;

John P. Meskell, Castleconnell, IE;

Colm Patrick Heffernan, Limerick, IE;

Mark Forde, Nenagh, IE;

Shane Geary, Sixmilebridge, IE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01); H10D 10/60 (2025.01); H10D 30/65 (2025.01); H10D 62/17 (2025.01); H10D 84/40 (2025.01);
U.S. Cl.
CPC ...
G01R 31/2608 (2013.01); H10D 10/60 (2025.01); H10D 30/65 (2025.01); H10D 62/393 (2025.01); H10D 84/409 (2025.01);
Abstract

The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.


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