The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Jan. 03, 2023
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Chih-Ping Chung, Hsinchu, TW;

Ming-Yu Ho, Taichung, TW;

Saysamone Pittikoun, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H10F 39/18 (2025.01);
U.S. Cl.
CPC ...
H10F 39/80377 (2025.01); H10F 39/014 (2025.01); H10F 39/024 (2025.01); H10F 39/026 (2025.01); H10F 39/182 (2025.01); H10F 39/805 (2025.01); H10F 39/8053 (2025.01); H10F 39/8057 (2025.01); H10F 39/8063 (2025.01); H10F 39/807 (2025.01);
Abstract

A 3D CMOS image sensor is provided in the present invention, including a semiconductor substrate, a photodiode and a well formed in the semiconductor substrate, a shallow trench isolation (STI) layer formed on a front surface of the semiconductor substrate, a fin protruding upwardly from the semiconductor substrate through the STI layer, wherein the fin is composed of the photodiode and the well, a first gate spanning the photodiode portion and the well portion abutting the photodiode portion of the fin to constitute a transfer transistor, a second gate spanning in the middle of the well portion of the fin to constitute a reset transistor, and a floating diffusion region in the well portion of the fin between the first gate and the second gate electrically connecting the transfer transistor and the reset transistor.


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