The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Sep. 18, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Hui Lu, Beijing, CN;

Yipeng Chen, Beijing, CN;

Shuai Xie, Beijing, CN;

Fei Fang, Beijing, CN;

Shuo Li, Beijing, CN;

Xuewei Tian, Beijing, CN;

Ling Shi, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/60 (2025.01); G09G 3/3233 (2016.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); G09G 3/3233 (2013.01); H10D 86/0221 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/021 (2013.01);
Abstract

A display substrate, a manufacturing method therefor, and a display apparatus are provided. The display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on an substrate. The first semiconductor layer includes active layers of a plurality of poly silicon transistors, the first conductive layer includes gates of a plurality of poly silicon transistors, a first electrode plate of a storage capacitor and a first scan signal line. The second conductive layer includes a second electrode plate of the storage capacitor. The second semiconductor layer includes active layers of a plurality of oxide transistors. The third conductive layer includes gates of the plurality of oxide transistors.


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