Phase-locked loop update cancellation

Abstract

A pulse limiter circuit of a phase-locked loop (PLL) receives, from a phase frequency detector of the PLL, first second input pulses, where pulse widths of the first and second input pulses indicate whether a reference clock signal leads or lags a feedback clock signal. The pulse limiter circuit determines whether a pulse width of the first or second input pulse is greater than a selected duration indicative of transient phase jitter. Based on determining the pulse width of the first or second input pulse is greater than the selected duration, the pulse limiter circuit sets a pulse width of a first output pulse equal to a pulse width of a second output pulse width and outputs the first and second output pulses to a charge pump of the PLL, such that no phase adjustment to the feedback clock signal is made based on the first and second input pulses.