The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2025
Filed:
Mar. 04, 2024
Qualcomm Incorporated, San Diego, CA (US);
Darshan Kumar Nandanwar, Bangalore, IN;
Siddesh Halavarthi Math Revana, Bangalore, IN;
Kuldeep Singh Chahal, Noida, IN;
Srinivasa Kumar Munivenkata Gowda, Bangalore, IN;
Nilesh Dhavlikar, Bangalore, IN;
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.