The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Nov. 29, 2021
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Meili Wang, Beijing, CN;

Xuan Liang, Beijing, CN;

Fei Wang, Beijing, CN;

Lei Wang, Beijing, CN;

Yafeng Yang, Beijing, CN;

Xue Dong, Beijing, CN;

Zhanfeng Cao, Beijing, CN;

Mingxing Wang, Beijing, CN;

Fuqiang Li, Beijing, CN;

Chenyang Zhang, Beijing, CN;

Xinxin Zhao, Beijing, CN;

Yanling Han, Beijing, CN;

Lei Wang, Beijing, CN;

Xuan Feng, Beijing, CN;

Yapeng Li, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 21/66 (2006.01); H10F 39/00 (2025.01); H10H 20/857 (2025.01); H10H 20/01 (2025.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 22/20 (2013.01); H10F 39/811 (2025.01); H10H 20/857 (2025.01); H10F 39/011 (2025.01); H10H 20/0364 (2025.01);
Abstract

A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a chip arranged on the base substrate, wherein the chip includes a chip main body and a plurality of terminals arranged on the chip main body; a terminal expansion layer arranged on the base substrate, the terminal expansion layer including a conductive material, and the terminal expansion layer and at least one terminal are located on a same side of the chip main body; and a plurality of expansion wires in the terminal expansion layer, wherein the plurality of expansion wires are electrically connected to the plurality of terminals, respectively, to lead out the plurality of terminals, wherein an orthographic projection of at least one expansion wire on the base substrate completely covers an orthographic projection of a terminal electrically connected to the expansion wire on the base substrate.


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