The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2025
Filed:
Apr. 10, 2023
Centre for Development of Advanced Computing (C-dac), Thiruvananthapuram, IN;
Indian Institute of Science (Iisc), Karnataka, IN;
Subhash Joshi Tharayparambil George, Kerala, IN;
Renji Varghese Chacko, Kerala, IN;
Akhila Elappully Manikandan, Kerala, IN;
Seena Somarajan, Kerala, IN;
Vinod John, Karnataka, IN;
Anurag Singh, Karnataka, IN;
CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING (C-DAC), Thiruvananthapuram, IN;
INDIAN INSTITUTE OF SCIENCE (IISC), Bangalore, IN;
Abstract
Present disclosure discloses a simple litz planar architecture using minimal vias for reducing Alternating Current (AC) resistance. The simple litz planar structure comprises a plurality of conductor strands of a first layer, a plurality of conductor strands of a second layer; and a plurality of vias set. The first layer and the second layer are separated by an insulating layer and each vias set is configured to perform transposition between a corresponding conductor strand of the first layer and a conductor strand of the second layer. The disclosed transposition method is simple, easy to manufacture and consequently, cost effective. The reduction in AC resistance obtained using disclosed simple litz planar structure is similar to planar litz winding. Further reduction in AC resistance is obtained by implementing multi-transposition per layer in the disclosed simple litz winding structure.