The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

May. 09, 2022
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ziyad Hakura, San Jose, CA (US);

Sriram Venkateshan, Bangalore, IN;

Sharad Raj, Bengaluru, IN;

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/00 (2011.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06T 15/005 (2013.01); G06T 1/20 (2013.01);
Abstract

In embodiments a graphics pipeline includes a logic that can assess whether to enable or disable tiled rendering for sets of graphics primitives. The logic applies one or more rules or heuristics to a set of graphics primitives associated with a frame, and determines whether to enable tiled rendering for that set of graphics primitives if the one or more rules or heuristics are satisfied. Otherwise, the logic determines to disable tiled rendering for that set of graphics primitives. As further graphics primitives are received for the frame, the logic may make additional decisions as to whether or not to render the further graphics primitives using tiled rendering.


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