The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2025
Filed:
Oct. 07, 2022
Samsung Electronics Co., Ltd., Suwon-si, KR;
Akio Misaka, Hwaseong-si, KR;
Noyoung Chung, Hwaseong-si, KR;
Taekyum Kim, Suwon-si, KR;
Sanghwa Lee, Seoul, KR;
Woonhyuk Choi, Hwaseong-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
A layout method of a semiconductor chip, includes designing a layout using a restriction rule such that a layout pattern having a length smaller than a first length in a first direction has to have a length smaller than a second length in a second direction, the second direction intersecting the first direction, generating a plurality of unit regions by partitioning the layout in the first direction, generating a plurality of target regions by adding a reference region to a partitioned edge of each of the plurality of unit regions, retargeting the plurality of target regions in parallel, and generating a correction layout by merging the plurality of retargeted target regions.