The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Jan. 23, 2024
Applicant:

Wenzhou University, Zhejiang, CN;

Inventors:

Pengjun Wang, Zhejiang, CN;

Li Ni, Zhejiang, CN;

Gang Li, Zhejiang, CN;

Hao Ye, Zhejiang, CN;

Cai Long Jin, Zhejiang, CN;

Assignee:

Wenzhou University, Zhejiang, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/75 (2013.01); H03K 19/0948 (2006.01); H03K 19/17704 (2020.01); H03K 19/17728 (2020.01); H03K 19/17764 (2020.01);
U.S. Cl.
CPC ...
G06F 21/75 (2013.01); H03K 19/0948 (2013.01); H03K 19/17764 (2013.01); H03K 19/17704 (2013.01); H03K 19/17728 (2013.01);
Abstract

A reconfigurable PUF with two PUF functions comprises 2×n PUF cells, a sequential control module, a row selection module, n amplification modules, n first bit lines, and n second bit lines. Each of the 2×n PUF cells comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor. The PUF cells can provide two independent responses, and can operate in a SRAM mode and an inverter mode. Therefore, the reconfigurable PUF with two PUF functions can operate both in the SRAM mode and the inverter mode, and a PUF operating mode with higher reliability is selected for generating final responses.


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