The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Apr. 07, 2023
Applicant:

Neuroblade Ltd., Tel Aviv, IL;

Inventors:

Eliad Hillel, Herzliya, IL;

Shany Braudo, Tel Aviv, IL;

Gal Dayan, Hod Hasharon, IL;

Shay Koren, Tel Aviv, IL;

Assignee:

NeuroBlade Ltd., Tel Aviv, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/16 (2006.01); G06F 9/50 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 16/75 (2019.01);
U.S. Cl.
CPC ...
G06F 13/1694 (2013.01); G06F 9/5016 (2013.01); G06F 11/1044 (2013.01); G06F 13/1668 (2013.01); G06F 13/404 (2013.01); G06F 17/16 (2013.01);
Abstract

Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums.


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