Cache circuit that selectively stores data blocks to dynamically optimize for read and write transactions

Abstract

A cache circuit includes read address registers to store memory addresses of data blocks requested in recent memory read transactions in a memory circuit and write address registers to store memory addresses of the data blocks recently written to the memory circuit. The cache circuit also includes data registers for storing data blocks corresponding to select memory addresses stored in the read address registers and the write address registers based on a pattern of recent memory transactions. The selection of memory addresses for which corresponding data blocks are stored in the data registers is based on a mode count that may be dynamically determined based on the memory addresses accessed in the most recent memory transactions. The mode count depends on whether a requested data block is stored in the data registers and whether the memory address is stored in the read address registers or the write address registers.