The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Sep. 19, 2022
Applicant:

Hewlett Packard Enterprise Development Lp, Spring, TX (US);

Inventors:

Jan Maximilian Mäder, Fort Collins, CO (US);

Christian Simmendinger, Baden-Württemberg, DE;

Tobias Walter Wolfgang Schiffmann, Baden-Württemberg, DE;

Torsten Wilde, Berlin, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 9/505 (2013.01); G06F 9/5044 (2013.01); G06F 11/3428 (2013.01); G06F 2201/80 (2013.01); G06F 2209/5019 (2013.01); G06F 2209/505 (2013.01);
Abstract

A method for optimizing operations of high-performance computing (HPC) systems includes collecting data associated with a plurality of workload performance profiling counters associated with a workload during runtime of the workload in an HPC system. Based on the collected data, the method includes using a machine-learning technique to classify the workload by determining a workload-specific fingerprint for the workload. The method includes identifying an optimization metric to optimize during running of the workload in the HPC system. The method includes determining an optimal setting for a plurality of tunable hardware execution parameters as measured against the optimization metric by varying at least a portion of the plurality of tunable hardware execution parameters. The method includes storing the workload-specific fingerprint, the optimization metric, and the optimal setting for the plurality of tunable hardware execution parameters as measured against the optimization metric in an architecture-specific knowledge database.


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