The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Jul. 10, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Anantha Sharma, Bengaluru, IN;

Pandi Kanniah, Bengaluru, IN;

Sharath Kumar Kodase, Bengaluru, IN;

Suman Prakash Balakrishnan, Bengaluru, IN;

Sandeep Kumar Ananthapalli, Bengaluru, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01);
Abstract

Example embodiments of the present disclosure disclose method and system for performing read/write operations in NAND memory. A memory controller of the NAND memory receives write request from host controller to write data present in set of support cell blocks of NAND memory into a 'n'-level cell block of NAND memory. The write request includes information about mapping between set of support cell blocks and ‘n’-level cell block. The mapping between set of support cell blocks and ‘n’-level cell block is used to update L2P table (). Further, memory controller performs copyback operation on set of support cell blocks for writing data to ‘n’-level cell block based on L2P table using NAND latches. On receiving read request, host controller retrieves data from at least one support cell block associated with ‘n’-level cell block based on mapping on determining ‘n’-level cell block is listed in active block list.


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