The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Mar. 02, 2021
Applicant:

Guangdong Zhineng Technology Co., Ltd., Guangdong, CN;

Inventor:

Zilan Li, Guangdong, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/04 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/10 (2025.01); H10D 62/40 (2025.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/475 (2025.01); H10D 30/015 (2025.01); H10D 62/117 (2025.01); H10D 62/405 (2025.01); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01);
Abstract

Provided are a semiconductor device and a method for manufacturing same. The device comprises: a substrate, a first insulating layer on the substrate, a plurality of trenches formed in the substrate, a nucleation layer arranged on one side wall of each trench, and a first semiconductor layer formed along the trenches by means of the nucleation layer. The present disclosure facilitates the achievement of one of the following effects: achieving a high height-width ratio and a high integration density, reducing an on-resistance, improving a threshold voltage, achieving a normally-off state, and providing a semiconductor device that has a high power and a high reliability, is suitable for a planarization process, is provided with an easy preparation method, and reduces costs.


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