The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Dec. 23, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ping-Chen Liu, Portland, OR (US);

Andy Lee, Sunnyvale, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H03K 19/094 (2006.01); H03K 19/177 (2020.01);
U.S. Cl.
CPC ...
H03K 19/1737 (2013.01); H03K 19/094 (2013.01); H03K 19/177 (2013.01);
Abstract

Systems and methods of the present disclosure may provide efficient power consumption for programmable logic devices based on unused portions of programmable logic. A programmable logic device includes a plurality of programmable logic sectors that implement a circuit design, unused portions of the programmable logic device, and interconnection resources. The interconnection resources include a multiplexer that receives a control signal and that generates an output signal based on the control signal and a driver that receives the output signal and that implements a low-power mode to reduce leakage current.


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