The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Jan. 19, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Ramaprasath Vilangudipitchai, San Diego, CA (US);

Rui Chen, Irvine, CA (US);

Seung Hyuk Kang, San Diego, CA (US);

Venugopal Boynapalli, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/40 (2015.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); H03K 3/012 (2013.01); H03K 19/20 (2013.01);
Abstract

A hybrid flop tray, including: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops of the set includes fin field effect transistors (FinFETs) each sized with a first number of fins, and a second subset of one or more of the flip-flops of the set includes FinFETs each sized with a second number of fins, wherein the first number of fins is different than the second number of fins; and a control circuit configured to provide control signals to the set of flip-flops.


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