Series capacitor buck converter and controller circuit and control method thereof

Abstract

Disclosed herein is a controller circuit of a series capacitor buck converter including input and output lines, a first switch, a coupled inductor including a first inductor and a second inductor, a second switch, a series capacitor, a third switch, a fourth switch, and an output capacitor. The controller circuit includes a control logic circuit that generates a plurality of control signals instructing ON-OFF states of the first to fourth switches so as to alternately repeat a first state in which the first switch and the fourth switch are ON and a second state in which the second switch and the third switch are ON, with an interval of dead time, and a first timing generator that generates a first timing signal as a trigger for turning on the first switch at a second dead time inserted into a period of transition from the second state to the first state.