The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2025
Filed:
Mar. 24, 2023
Mitsubishi Electric Research Laboratories, Inc., Cambridge, MA (US);
Hongbo Sun, Cambridge, MA (US);
Imtiaj Khan, Cambridge, MA (US);
Kyeong Jin Kim, Cambridge, MA (US);
Jianlin Guo, Cambridge, MA (US);
Mitsubishi Electric Research Laboratories, Inc., Cambridge, MA (US);
Abstract
Disclosed is a method and system for identifying an existence, location and type of a weak-signal fault in an islanded inverter-based microgrid. The weak-signal fault includes a high impedance fault, an inverter DC-side short-circuit fault, and an inverter tripping fault, and usually fails to be detected by conventional relay methods due to small magnitude of fault current. Upon received voltage and current measurements from intelligent electronic devices installed in the microgrid, the variation mode decomposition algorithm is firstly applied to detect the existence of fault based on denoised time series of measurements using discrete wavelet transform algorithm. After detecting the presence of fault, the correlation-based matrix is applied to locate the suspicious fault locations, and then K-nearest neighbors model is utilized to identify the faulty branch among those locations using dynamic time warping algorithm to measure the distance between neighbors. Following fault localization, fault classification is done by observing sequence components and phasor measurements and feeding the observational inputs to a fault classification logic circuit model.