The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Jul. 06, 2022
Applicant:

Murata Manufacturing Co., Ltd., Nagaokakyo, JP;

Inventors:

Frédéric Voiron, Barraux, FR;

Brigitte Soulier, Grenoble, FR;

Hiroshi Nakagawa, Caen, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/32139 (2013.01);
Abstract

A method of fabricating a semiconductor structure that includes: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.


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