Row decoder circuit, memory device and memory system

Abstract

A row decoder circuit includes a first transistor connected to a power supply node and a first node; a plurality of second nodes connected in parallel between the first node and a power ground node, each of the plurality of second nodes being connected to a corresponding word line among the plurality of word lines; a plurality of second transistors connected between the first node and the plurality of second nodes; a plurality of third transistors connected between the plurality of second nodes and a power ground node; a comparator outputting a detection signal by receiving a voltage of the first node and a reference voltage. In a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the third transistors are turned off, so that the first node and the plurality of second nodes are charged. In a development period, the first transistor maintains a turned-on state, the plurality of second transistors are turned off, and each of the second nodes is discharged at a different rate depending on whether current of the corresponding word line is leaked, and in a sensing period, the first transistor is turned off, the plurality of second transistors are turned on, and the first node is selectively discharged according to voltage levels of the discharged second nodes.