The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2025
Filed:
Dec. 07, 2021
University of Cincinnati, Cincinnati, OH (US);
John Martin Emmert, Dayton, OH (US);
University of Cincinnati, Cincinnati, OH (US);
Abstract
A system comprises an nMOS active resistor, nMOS transistors, a pMOS active resistor, and pMOS transistors, wherein a subset of the nMOS transistors a subset of the pMOS transistors are coupled to each other, respectively, according to a parallel OR configuration, a source terminal of the nMOS active resistor is coupled to respective drain terminals of the nMOS transistors, and a source terminal of the pMOS active resistor is coupled to respective drain terminals of the pMOS transistors. The transistor level delay based circuit further includes a write subcircuit component includes one of the nMOS transistors coupled to at least one of the pMOS transistors, wherein the write subcircuit is controlled by reverse logic signals, and a gate component includes an additional subset of the plurality of nMOS transistors coupled to an additional subset of the pMOS transistors, the gate component corresponding to a semistatic cross coupled inverter circuit.