The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Jul. 19, 2023
Applicant:

Raytheon Company, Waltham, MA (US);

Inventors:

Micky Harris, Lompoc, CA (US);

Magathi J. Willis, Broomfield, CO (US);

Assignee:

RAYTHEON COMPANY, Tewksbury, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01);
Abstract

An interface BIT failure detection circuit includes a sequencing circuit and a multiplexer. The sequencing circuit configured to generate the sequence selection signal. The multiplexer is in signal communication with the sequencing circuit, and includes a plurality of interface input. Each interface input corresponds to an interface of a device under test. The sequence selection signal is configured to control the MUX to sequentially select each of the interface inputs. The MUX includes an output terminal configured to output a test signal configured to indicate whether or not at least one fault corresponding to one or more of the interface inputs or a main power supply exists.


Find Patent Forward Citations

Harris, Micky. (2025). Interface built in test failure detection apparatus (U.S. Patent No. 12429518). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12429518

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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