The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

May. 27, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Hongting Lu, Beijing, CN;

Baolei Huo, Beijing, CN;

Kuo Sun, Beijing, CN;

Yuhsiung Feng, Beijing, CN;

Linqian Han, Beijing, CN;

Yangpeng Wang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/129 (2023.01); H10K 50/824 (2023.01); H10K 50/828 (2023.01); H10K 59/131 (2023.01); H10K 59/80 (2023.01);
U.S. Cl.
CPC ...
H10K 59/129 (2023.02); H10K 50/824 (2023.02); H10K 50/828 (2023.02); H10K 59/131 (2023.02); H10K 59/80522 (2023.02); H10K 59/80524 (2023.02);
Abstract

The present disclosure provides a display substrate and a display device. The display substrate includes: a driver chip, a display area and a peripheral area surrounding the display area, the driver chip is located in the peripheral area, the driver chip is close to a first side of the display area; the display substrate further includes: a cathode layer extending from the display area to the peripheral area; a cathode auxiliary layer extending from the display area to the peripheral area, and the cathode auxiliary layer is coupled to the cathode layer in the display area; a power line layer located in the peripheral area, the power line layer includes a first power line pattern, and the first power line pattern is close to the first side of the display area; the first power line pattern is coupled to the cathode auxiliary layer.


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